1. Field of the Invention
This disclosure relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device having separated and independent gate patterns with minute thicknesses.
2. Description of the Related Art
Generally, a semiconductor memory device is classified into dynamic random access memory (DRAM) and static random access memory (SRAM) in accordance with data storing method. An SRAM device has many advantages such as a high operating speed, low power consumption, and simplified operation, thus it has been the focus of intense interest in recent years. In addition, the SRAM device is also advantageous because no refresh is needed for storing data as compared with a DRAM.
In general, a SRAM device may include a pair of pull-down transistors (hereinafter, referred to as driving transistors), a pair of pass transistors, and a pair of pull-up transistors. The SRAM device may also be classified as a full complementary metal oxide semiconductor (CMOS) type, a high load resistor (HLR) type, and a thin film transistor (TFT) type in accordance with a structure of the pull-up transistor.
The full CMOS type SRAM uses a P-channel bulk MOSFET as a pull-up device, and the HLR type SRAM uses a high resistive polysilicon layer as a pull-up device. Further, the TFT type SRAM uses a P-channel polysilicon TFT as a pull-up device. The full CMOS type SRAM has the advantages of a low standby current and a steady operation as compared with the other types of SRAM.
FIG. 1 is a circuit diagram of a conventional full CMOS type SRAM.
As shown in FIG. 1, a cell of a conventional SRAM includes first and second pass transistors Q1 and Q2, a first P-MOS transistor Q5, and a first N-MOS transistor Q3. The first pass transistor Q1 electrically connects a first bit line BL1 with a first memory cell node Nd1, and the second pass transistor Q2 electrically connects a second bit line BL2 with a second memory cell node Nd2. The first P-MOS transistor Q5 is electrically interconnected between a power source voltage Vcc and the first memory cell node Nd1, and the first N-MOS transistor Q3 is electrically interconnected between a base voltage Vss and the first memory cell node Nd1. The first P-MOS transistor Q5 and the first N-MOS transistor Q3 are selectively operated in accordance with a signal of the second memory cell node Nd2, thus the power source voltage Vcc or the base voltage Vss is selectively applied to the first memory cell node Nd1.
The cell of a conventional SRAM further includes a second P-MOS transistor Q6 and a second N-MOS transistor Q4. The second P-MOS transistor Q6 is electrically interconnected between the power source voltage Vcc and the second memory cell node Nd2, and the second N-MOS transistor Q4 is electrically interconnected between a base voltage Vss and the second memory cell node Nd2. The second P-MOS transistor Q6 and the second N-MOS transistor Q4 are selectively operated in accordance with a signal of the first memory cell node Nd1, thus the power source voltage Vcc or the base voltage Vss is selectively applied to the second memory cell node Nd2.
One of the first pass transistors Q1, one of the driving transistors Q3, and one of the pull-up transistors Q5 are electrically interconnected with one another at the first memory cell node Nd1. Another pass transistor Q2, another driving transistor Q4, and another pull-up transistor Q6 are electrically interconnected with one another at the second memory cell node Nd2.
As described above, the conventional full CMOS type SRAM includes a number of N-MOS transistors Q1, Q2, Q3, and Q4 as well as a number of P-MOS transistors Q5 and Q6. As a result, the transistors of the SRAM cannot be formed into a lined gate structure such as the gate structure of the cell of a DRAM or a non-volatile memory (NVM). Thus, each of the transistors in the cell of the conventional full CMOS type SRAM is formed as an independent pattern separated from each other, which is called an island pattern as compared with the DRAM or the NVM.
A gate electrode of the transistor in the SRAM is formed at a portion of an active region of a wafer with which the gate pattern is overlapped, thus the gate pattern needs to be sufficiently long enough to overlap with the active region in order that an effective length of the gate is not reduced in operation of the SRAM. However, when the gate pattern is formed by a conventional photolithography process, a peripheral portion of the gate pattern is formed to be a round shape.
FIG. 2 is a plan view illustrating a number of conventional separated gate patterns.
Referring to FIG. 2, a number of rectangular active regions 10 is defined on the wafer, and gate patterns 12 overlap the active regions 10. However, the overlapping area of the active region 10 is reduced at the peripheral portion A of the gate pattern 12. Thus, a channel region for passing electrons is narrowed at the peripheral portion A of the gate pattern 12, thereby generating an operating failure of the transistor.
To minimize the operating failure of the transistor, the gate patterns 12 are sufficiently long to overlap with the active regions 10. That is, the gate pattern 12 is lengthened to extend the active region 10 such that the rounded peripheral portion A of the gate pattern 12 is not positioned over the active region 10. However, the trend towards increasing degrees of integration in a SRAM device has gradually reduced a processing margin M for the overlap of the gate pattern 12 with the active region 10, thus the gate patterns of conventional SRAM devices manufactured according to minute design rules are typically formed by a trim mask process.
FIGS. 3A to 3D are perspective views illustrating the processing steps of a conventional method for manufacturing a gate of the SRAM device using a conventional trim mask. In FIGS. 3A to 3D, a three dimensional Cartesian coordinate system is introduced with an x-direction as a longitudinal direction of the substrate, a y-direction as a latitudinal direction of the substrate and a z-direction as a height direction of the substrate.
Referring to FIG. 3A, an active region is defined by a field region 52 on a surface portion of the substrate 50. A gate oxide layer 54, a polysilicon layer 56, and a hard mask layer 58 are sequentially coated on the substrate 50.
Referring to FIG. 3B, the hard mask layer 58 is partially etched away in an area corresponding to the field region 52, leaving an opening portion 581a having a predetermined depth along the y direction and a predetermined width along the x direction. As a result, a trim mask 58a is formed on the polysilicon layer 56 for separating the polysilicon layer 56 according to the active region, and the polysilicon layer 56 is partially exposed through an opening portion 581a of the trim mask 58a. 
Referring to FIG. 3C, a photoresist pattern 60 for patterning the polysilicon layer 56 is formed on surfaces of the trim mask 58a and the exposed polysilicon layer 56. A photoresist layer is coated on surfaces of the trim mask 58a and the exposed polysilicon layer 56, and is exposed by light having a predetermined wavelength along the x direction, perpendicular to the opening portion 581a of the trim mask 58a. Then, a developer is supplied on the exposed photoresist layer to thereby form the photoresist pattern 60 that exposes the opening portion 581a of the trim mask 58a along the x direction of the substrate 50.
When the exposed photoresist layer is developed on the trim mask 58a, the developer dissolves the photoresist layer, and comes into direct contact with the polysilicon layer 56 since the polysilicon layer 56 is exposed through the opening portion 581a of the trim mask 58a. As a result, an etching characteristic of the polysilicon layer 56 is changed by the developer. Specifically, the developer isotropically diffuses and permeates into the polysilicon layer 56, thus an etching characteristic of a neighboring polysilicon layer adjacent to the exposed polysilicon layer 56 is changed along with the exposed polysilicon layer 56. For example, the etching rate of the exposed polysilicon layer is increased due to the developer.
Referring to FIG. 3D, the trim mask 58a is partially etched away using the photoresist pattern as an etching mask 60 along the x direction, so that the trim mask 58a is separated by a channel running in the x direction to form a number of hard mask patterns 62 that are separated along the y direction. Next, the polysilicon layer 56 is partially etched away using the hard mask patterns 62 as etching masks to thereby form the gate patterns 56a. The gate patterns 56a are independently formed according to the active region and separated along the y direction of the substrate 50.
The polysilicon layer 56 exposed by the opening portion 58 1a of the trim mask 58a has a higher etching rate than the other portion thereof, thus the polysilicon layer 56 adjacent to the opening portion 581a is usually over-etched by the developer. Accordingly, even the polysilicon layer corresponding to the active region is etched away during the etching process of the exposed polysilicon layer 56, the gate pattern 56a may be broken and an operation failure may be generated.
Embodiments of the invention address these and other disadvantages of the conventional art.